A data output buffer is generally used in an integrated circuit device such as a semiconductor memory device, to change a CMOS level of data generated on the integrated circuit into a level which is suitable to drive another device external to the integrated circuit. It is well known that due to loading of a data output pin, the data output buffer consumes a large amount of current. Moreover, as the power supply voltage used in the integrated circuit decreases, the output speed of the data buffer generally decreases.
In order to enhance the output speed of the data buffer, it is known to boost a high level data signal in a data output buffer. Although this technology can enhance the transmission speed of the data, it may increase the current consumption of the output buffer. This may cause data output noise which may degrade the operation of the semiconductor memory device. To solve this problem, it is known to use a boosted high level data signal and to clamp the boosted signal.
FIG. 1 shows a prior data output buffer as described above. A data output circuit 10, which receives a pair of data signals DO and DO and outputs a data output signal DOUT, is controlled by a data output activation signal .phi.DOE. A signal .phi.X, provided from the data output circuit 10 to a clamp circuit 70, drives a pull-down transistor in the clamp circuit 70. A boosting data signal DOK is boosted by the data output circuit 10 and then transmitted to the clamp circuit 70. The potential of the boosting data signal is clamped by the clamp circuit 70, and affects the level of the data output signal DOUT.
FIG. 2A is a circuit diagram showing the data output circuit 10 of FIG. 1. In FIG. 2A, the data output activation signal .phi.DOE controls the operation of the data output circuit 10. Upon transition of the data output activation signal .phi.DOE to a logic "high" level, the data signals DO and DO are input to NAND gates 4 and 6, respectively. If the data which is read out from the memory or other integrated circuit is "1", the data signal DO stays at the logic "high" level, whereas the inverted data signal DO stays at the logic "low" level. Thus, with the transition of the potential of a node 39 to a logic "high" level, the potential of the node 25, from which an initial boosting data signal DOKI is generated, becomes Vcc+2Vth (where Vth is a threshold voltage of an NMOS transistor), due to NMOS capacitor 24. The node 25 was precharged to the Vcc level when the data output activation signal .phi.DOE was at a logic "low" level. Since the output node 38 of the NAND gate 2 is at the logic "low" level, the PMOS transistor 26 is turned on, thereby causing the boosting data signal DOK to follow the initial boosting data signal DOKI at Vcc+2Vth.
FIG. 2B shows the clamp circuit 70 of FIG. 1. Referring to FIG. 2B, the boosting data signal DOK, which is output from the data output circuit 10 of FIG. 2A, is clamped by charge sharing with an NMOS capacitor 21 through a PMOS transistor 17. The data output signal DOUT follows the boosting data signal DOK which has been clamped as described above.
However, in a semiconductor memory device or other integrated circuit which uses a low voltage power supply voltage Vcc, such as 3.3 volts, the PMOS transistor 17 in FIG. 2B may be turned on before the boosting data signal DOK is sufficiently boosted. That is, even though the power supply voltage of 3.3 volts is applied to the gate of the PMOS transistor 17, the PMOS transistor 17 may be turned on by the boosted potential of the boosting data signal DOK which is applied to a source thereof. This may degrade the transition speed of the data output signal DOUT. Consequently, it may be difficult to obtain a stable, high level data output signal DOUT, since the data output signal DOUT follows the boosting level of the boosting data signal DOK, and the boosting data signal DOK is clamped before reaching a sufficient boosting level.